As complementary metal oxide silicon (CMOS) devices are scaled down to have feature sizes below 0.5 micrometers (.mu.m), several considerations become increasingly important.
One important consideration is latch-up. Latch-up is defined as a high current state which is triggered upon certain electrical excitations. The high current state generates heat which can cause failure of the semiconductor device. Thus, it is desirable to design semiconductor devices with latch-up immunity.
FIG. 1 is a cross-sectional view of a prior art semiconductor device 8 which is susceptible to latch-up. Semiconductor device 8 includes an n-type silicon substrate 10 having a p-well 12 and an n-well 14. P-well 12 and n-well 14 are separated by a boundary region 26. Formed within p-well 12 are n.sup.+ source/drain regions 16, 18 and p.sup.+ contact region 28 which is connected to a first voltage source V.sub.ss (typically ground). Formed within n-well 14 are p.sup.+ source/drain regions 20, 22 and n.sup.+ contact region 30 which is connected to a second voltage source V.sub.DD (typically 3.3 volts (V) or 5.0 V). A field oxide structure 24 is formed at the surface of substrate 10 overlying boundary region 26. Gate structures G1 and G2, each comprising, for example, a gate electrode and an underlying gate oxide layer, complete n-channel metal oxide semiconductor field effect transistor (MOSFET) 32 and p-channel MOSFET 34, respectively.
Latch-up occurs when parasitic bipolar transistors located within semiconductor device 8 are connected in a positive feedback loop. A parasitic vertical NPN bipolar transistor Q1 is formed by n-type source/drain regions 16, 18, p-well 12 and n-type substrate 10. A parasitic lateral NPN bipolar transistor Q2, which is formed in parallel with vertical NPN bipolar transistor Q1, is formed by n-type source/drain regions 16, 18, p-well 12 and n-well 14. A lateral parasitic PNP transistor Q3 is formed by p-type source/drain regions 20, 22, n-well 14 and p-well 12.
FIG. 2 is a diagram of the latch-up circuit of semiconductor device 8. Lateral NPN bipolar transistor Q2 is not shown for purposes of clarity. However, it is understood that lateral NPN bipolar transistor Q2 is in parallel with vertical NPN bipolar transistor Q1.
As shown in FIG. 2, the emitter of Q1 is coupled through a resistor R1 to the base of Q1. The emitter of Q3 is coupled through a resistor R2 to the base of Q3. The collector of Q1 is coupled to the base of Q3 and the collector of Q3 is coupled to the base of Q1.
Latch-up occurs when the voltage drop across resistor R2, hence the voltage drop between the emitter and base of Q3, is sufficient to turn Q3 on. This causes current flow between the emitter and collector of Q3. This produces a voltage drop across resistor R1, hence a voltage drop between the emitter and base of Q1. If the voltage drop between the emitter and base of Q1 is sufficient, then Q1 turns on. This causes current flow between the emitter and collector of Q1 which increases the current flow through resistor R2. This increases the voltage drop between the emitter and base of Q3. The positive feedback loop continues resulting in latch-up.
By decreasing the values of resistors R1 and R2, any tendency to forward bias (create a voltage drop between the emitter and base) parasitic bipolar transistors Q1, Q3 is reduced and latch-up immunity is improved. Although lateral parasitic NPN bipolar transistor Q2 is not shown in FIG. 2, it is understood that latch-up has both a vertical and lateral component. Thus to effectively suppress latch-up, both vertical and lateral latch-up must be suppressed.
One conventional method to suppress latch-up is to form a p-type heavily doped region at the lower portion of p-well 12. Referring to FIG. 3, a mask 40, made of photoresist, is formed overlying n-well 14 and partially overlying field oxide structure 24. As shown, the angle formed by the intersection of edge 40a of mask 40 and the top 24a of field oxide structure 24 is 90.degree.. Mask 40 does not extend over p-well 12. The structure is then subjected to a high energy implant of a p-type impurity, shown as B.sup.+ for boron. The p-type impurity does not pass through mask 40 into n-well 14. However, the p-type impurity is introduced into a region A of p-well 12 at a depth below the upper surface of n-type substrate 10.
Since higher concentrations of dopants improve conductivity, the heavily doped region A exhibits relatively high conductance (low resistance). Referring to FIG. 1, by forming a p-type heavily doped region (shown as A1) in p-well 12, vertical latch-up in parasitic vertical NPN bipolar transistor Q1 is inhibited. However, the heavily doped region A1 does not inhibit lateral latch-up under the field oxide structure 24 due to the parasitic lateral transistors Q2, Q3. As feature size in semiconductor devices is further reduced, lateral latch-up becomes increasingly important. Thus it is desirable to have a method of manufacturing a semiconductor device which inhibits both vertical and lateral latch-up.
Another important consideration in semiconductor technology is interwell isolation, i.e. it is important to prevent current leakage between the n-well and p-well. Interwell isolation can further be broken down into n-type source/drain region to n-well isolation (n.sup.+ to n-well isolation) and p-type source/drain region to p-well isolation (p.sup.+ to p-well isolation). As feature size in semiconductor devices is further reduced and the n.sup.+ to n-well (and p.sup.+ to p-well) spacing decreases, interwell isolation becomes increasingly important.
Hayden et al., "A high-performance half-micrometer generation semiconductor technology for fast SRAM's", IEEE transactions on electron devices, 38:877-878 (1991) discusses using a plug implant to improve interwell isolation. FIG. 4 illustrates the formation of a p-type plug 48 within p-well 12. As shown in FIG. 4, a mask (46, 46a) is patterned to expose a narrow slit 47 overlying p-well 12 near boundary region 26. A high energy boron implant is performed, which passes p-type impurities through field oxide 24, to form a p-type heavily doped plug 48 near boundary region 26.
The p-type heavily doped plug 48 improves n.sup.+ to n-well isolation without significantly degrading p.sup.+ to p-well isolation. However, the plug implant does not significantly improve latch-up because of vertical latch-up in parasitic vertical NPN bipolar transistor Q1. Further, the plug implant method limits the minimum spacing between n.sup.+ source/drain region 18 and p.sup.+ source/drain region 20 and requires an additional masking step, both of which are disadvantageous.
FIG. 5 illustrates the formation of a semiconductor device 49 having a Buried Implanted Layer for Lateral Isolation (BILLI). A photoresist mask 50 is patterned over a portion of a p-type substrate 48 and over a portion of field oxide structure 24. As shown, the angle of intersection between edge 50a of mask 50 and the top 24a of field oxide structure 24 is 90.degree.. The structure is subjected to n-type impurity implantation(s) (not shown) to form n-well 52 (the n-type impurity does not pass through photoresist mask 50) and define p-well 12. The structure is then subjected to high energy implantation(s) using a p-type impurity, which passes p-type impurities through photoresist mask 50 into p-well 12 and also introduces p-type impurities into n-well 52 to form p-type dopant region 54. As shown, the portion 56 of dopant region 54 is located near the surface of p-well 12. The n-type source/drain regions are subsequently formed in portion 56 to form the n-channel MOSFET.
The dopant concentration in portion 56 determines the threshold voltage (the voltage applied to the gate at which the channel between the source and the drain becomes conductive) of the subsequently formed n-channel MOSFET, and hence semiconductor device 49. Since the dopant concentration in portion 56 depends upon the thickness of photoresist mask 50, the thickness of photoresist mask 50 determines the threshold voltage of semiconductor device 49. Since photoresists used to form photoresist mask 50 have poor conformality for different size devices (large variations in thickness depending upon the device dimensions), the BILLI method increases the tolerance for threshold voltage which is undesirable. (It is desirable to reduce any variation in threshold voltage between semiconductor devices, i.e. to reduce threshold voltage tolerances). Also, the BILLI method does not inhibit latch-up in parasitic lateral transistor Q2. In fact, the p-type dopant region 54 has a tendency to decrease the effective P.sup.+ to p-well spacing and thus enhances latch-up in parasitic lateral transistor Q2. Thus, the art needs a method for improving both vertical and lateral latch-up immunity and interwell isolation which does not have an adverse effect on threshold voltage tolerance.